Method for fabricating multi-chip semiconductor package

ABSTRACT

A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

FIELD OF THE INVENTION

The present invention relates to multi-chip semiconductor packages andfabrication methods thereof, and more particularly, to a multi-chipsemiconductor package with a packaged chip and a flip chip beingincorporated on a substrate, and a method of fabricating thesemiconductor package.

BACKGROUND OF THE INVENTION

In accordance with electronic products being developed with compactsize, light weight and high efficiency, semiconductor packages have beencorrespondingly reduced in profile and preferably incorporated withmultiple chips to be suitable for use with the electronic products. Suchstructure with multiple semiconductor chips being mounted in a singlepackage is customarily referred to as a multi-chip semiconductorpackage, wherein the multiple chips can be vertically stacked on a chipcarrier (such as a substrate or lead frame) or individually attached tothe substrate. The multi-chip package structure has a primary advantagefor providing the semiconductor package with effectively enhanced ormultiplied electrical and operational performances, making it suitablyused in the highly efficient electronic product.

U.S. Pat. Nos. 5,696,031 and 5,973,403 have disclosed a multi-chipsemiconductor package. Referring to FIG. 5, in this semiconductorpackage, a first chip 21 is mounted on a surface of a substrate 20 in aflip-chip manner that an active surface 210 of the first chip 21 facesdownwards and is electrically connected to the substrate 20 via aplurality of solder bumps 22. Then, a second chip 23 is attached to anon-active surface 211 of the first chip 21 and is electricallyconnected to the substrate 20 via a plurality of bonding wires 24. Anencapsulation body 25 is formed on the substrate 20 to encapsulate thefirst chip 21, second chip 23 and bonding wires 24. Finally, a pluralityof solder balls 26 are implanted on an opposite surface of the substrate20. This completes fabrication of the multi-chip semiconductor package.Since the wire-bonding process performed on the second chip 23 wouldgenerate shocks that may cause cracks of the solder bumps 22, anunderfill process is carried out between the first chip 21 and thesubstrate 20 to fill an insulating material (such as a resin material,etc.) in gaps between the adjacent solder bumps 22, so as to enhance themechanical strength of the solder bumps 22 and prevent them from cracksdue to the shocks generated by the wire-bonding process.

However, during the underfill process for the above semiconductorpackage, the procedure of filling the insulating material may easilycontaminate predetermined positions (such as bond fingers) on thesubstrate for connecting the bonding wires, and the bonding wires cannotbe fly bonded to the contaminated bond fingers, such that the yield ofthe wire-bonding process and the quality of electrical connectionbetween the second chip and the substrate would be degraded, and thereliability of the entire semiconductor package is thus deteriorated.Moreover, for the second chip that is electrically connected to thesubstrate via the bonding wires, since the second chip is directlyincorporated in the semiconductor package with the quality and yield ofthe second chip being unknown, a known good die (KGD) issue is produced.In other words, if the second chip not passing a burn-in test incursquality defects, the entire package having such second chip would failand the product yield is reduced.

U.S. Patent Publication No. 2004/0113275 has disclosed anothermulti-chip semiconductor package. As shown in FIG. 6, this semiconductorpackage allows a first chip 31 to be mounted on a surface of a substrate30 in a flip-chip manner, wherein an active surface 310 of the firstchip 31 faces downwards and is electrically connected to the substrate30 via a plurality of solder bumps 32. An insulating material (such as aresin material, etc.) is filled in gaps between the adjacent solderbumps 32 using an underfill technique. Then, a land grid array (LGA)package structure 33 is attached to a non-active surface 311 of thefirst chip 31 in an inverted manner, and a substrate 330 of the LGApackage structure 33 is electrically connected to the substrate 30 via aplurality of bonding wires 34. An encapsulation body 35 is formed on thesubstrate 30 to encapsulate the first chip 31, LGA package structure 33and bonding wires 34. Finally, a plurality of solder balls 36 areimplanted on an opposite surface of the substrate 30. This completesfabrication of the multi-chip semiconductor package.

Although the above fabrication method may solve the KGD problem, themulti-chip semiconductor package shown in FIG. 6 still have the similardrawback to that shown in FIG. 5. As the underfill process is requiredto fill the gaps between the adjacent solder bumps 32 with theinsulating material so as to enhance the mechanical strength of thesolder bumps 32 and prevent them from cracks due to shocks during thewire-bonding process, the procedure of filling the insulating materialmay easily contaminate predetermined positions (such as bond fingers) onthe substrate 30 for connecting the bonding wires 34, and the bondingwires 34 cannot be firmly bonded to the contaminated bond fingers,thereby degrading the yield of the wire-bonding process and the qualityof electrical connection between the LGA package structure 33 and thesubstrate 30, as well as deteriorating the reliability of the entiresemiconductor package.

Therefore, the problem to be solved here is to provide a multi-chipsemiconductor package, which can prevent predetermined positions forelectrical connection on a substrate from contamination and eliminate aKGD issue so as to assure the reliability and yield of the semiconductorpackage.

SUMMARY OF THE INVENTION

In light of the above drawbacks in the prior art, an objective of thepresent invention is to provide a multi-chip semiconductor package and afabrication method thereof, which do not require an underfill process,such that predetermined positions for electrical connection on asubstrate can be prevented from contamination, and the electricalconnection quality and reliability of the semiconductor package areassured.

Another objective of the present invention is to provide a multi-chipsemiconductor package and a fabrication method thereof, wherein apreformed package structure passing a burn-in test is incorporated inthe semiconductor package, such that a known good die (KGD) issue can beeliminated, and the reliability and yield of the semiconductor packageare assured.

A further objective of the present invention is to provide a multi-chipsemiconductor package and a fabrication method thereof, with a thermallyconductive adhesive being applied between an upper packaged chip and alower flip chip in the semiconductor package, such that heat generatedby the upper chip can be transmitted to the lower chip and then to asubstrate to be dissipated out of the semiconductor package, therebyeffectively improving the heat dissipating efficiency of thesemiconductor package.

In accordance with the above and other objectives, the present inventionproposes a multi-chip semiconductor package, comprising a substratehaving an upper surface and a lower surface opposed to the uppersurface; at least one first chip having an active surface and anon-active surface, wherein the active surface of the first chip ismounted on and electrically connected to the upper surface of thesubstrate via a plurality of solder bumps; a preformed package structurecomprising a lead frame, at least one second chip mounted on andelectrically connected to the lead frame, and a first encapsulation bodyfor encapsulating the second chip and a portion of the lead frame,wherein outer leads of the lead frame are exposed from the firstencapsulation body and mounted on the upper surface of the substrate,such that the first encapsulation body, the exposed outer leads and thesubstrate form a space where the first chip is received, and a gap ispresent between the non-active surface of the first chip and the firstencapsulation body; a second encapsulation body formed on the uppersurface of the substrate to encapsulate the first chip, the solder bumpsand the preformed package structure; and a plurality of solder ballsimplanted on the lower surface of the substrate. The present inventionalso proposes a fabrication method of the above multi-chip semiconductorpackage, comprising the steps of: preparing a substrate having an uppersurface and a lower surface opposed to the upper surface; providing atleast one first chip having an active surface and a non-active surface,and allowing the active surface of the first chip to be mounted on andelectrically connected to the upper surface of the substrate via aplurality of solder bumps; mounting a preformed package structure on theupper surface of the substrate, the preformed package structurecomprising a lead frame, at least one second chip mounted on andelectrically connected to the lead frame, and a first encapsulation bodyfor encapsulating the second chip and a portion of the lead frame,wherein outer leads of the lead frame are exposed from the firstencapsulation body and mounted on the upper surface of the substrate,such that the first encapsulation body, the exposed outer leads and thesubstrate form a space where the first chip is received, and a gap ispresent between the non-active surface of the first chip and the firstencapsulation body; forming a second encapsulation body on the uppersurface of the substrate to encapsulate the first chip, the solder bumpsand the preformed package structure; and implanting a plurality ofsolder balls on the lower surface of the substrate.

The above multi-chip semiconductor package can also be fabricated by abatch method comprising the steps of: providing a substrate stripcomprising a plurality of substrates and having an upper surface and alower surface opposed to the upper surface; mounting at least one firstchip on the upper surface of each of the substrates, the first chiphaving an active surface and a non-active surface, and allowing theactive surface of the first chip to be mounted on and electricallyconnected to the upper surface of each of the substrates via a pluralityof solder bumps; mounting a preformed package structure on the uppersurface of each of the substrates, the preformed package structurecomprising a lead frame, at least one second chip mounted on andelectrically connected to the lead frame, and a first encapsulation bodyfor encapsulating the second chip and a portion of the lead frame,wherein outer leads of the lead frame are exposed from the firstencapsulation body and mounted on the upper surface of each of thesubstrates, such that the first encapsulation body, the exposed outerleads and the corresponding substrate form a space where the first chipis received, and a gap is present between the non-active surface of thefirst chip and the first encapsulation body; forming a secondencapsulation body on the upper surface of the substrate strip toencapsulate all of the first chips, the solder bumps and the preformedpackage structures; implanting a plurality of solder balls on the lowersurface of the substrate strip; and performing a singulation process tocut the second encapsulation body and the substrate strip so as toseparate apart the plurality of substrates and form a plurality ofindividual semiconductor packages.

The second chip in the preformed package structure is electricallyconnected to the lead frame via a plurality of bonding wires. The leadframe comprises a die pad and a plurality of leads, wherein each of theleads is composed of an inner lead and an outer lead. The second chip ismounted on an upper surface of the die pad and electrically connected tothe inner leads. The inner leads and the bonding wires are encapsulatedby the first encapsulation body. In one preferred embodiment, the diepad is encapsulated by the first encapsulation body, and the gap betweenthe first chip and the first encapsulation body is filled with thesecond encapsulation body. In another preferred embodiment, a lowersurface of the die pad is exposed from the first encapsulation body andabuts against the gap between the first chip and the first encapsulationbody, such that a thermally conductive adhesive is filled in the gapbetween the first chip and the first encapsulation body prior tofabrication of the second encapsulation body.

The above multi-chip semiconductor package and its fabrication methodsallow a substrate to accommodate both a packaged chip and a flip chip.This is accomplished by firstly, electrically connecting a first chip ina flip-chip manner to the substrate via a plurality of solder bumps, andthen mounting a preformed package structure on the substrate, whereinthe preformed package structure is incorporated with a second chip andhas exposed outer leads that are mounted and electrically connected tothe substrate by surface mount technology (SMT), such that a firstencapsulation body of the preformed package structure, the exposed outerleads and the substrate form a space where the first chip is received,and the first encapsulation body is supported above the first chip, witha gap being present between the first encapsulation body and the firstchip. Since the preformed package structure is electrically connected tothe substrate by the surface mount technology, the solder bumps locatedbetween the first chip and the substrate would not subject to crackscaused by shocks generated during a wire-bonding process in the priorart. Thus, an underfill process is not required in the present inventionto fill gaps between the adjacent solder bumps located between the firstchip and the substrate. On the other hand, in the present invention, asingle molding process is carried out to form a second encapsulationbody for encapsulating the first chip and the preformed packagestructure as well as filling the gap between the first encapsulationbody and the first chip and the gaps between the adjacent solder bumps.This can prevent predetermined positions on the substrate for mountingthe outer leads of the preformed package structure from contamination bythe underfill process, and assure the preformed package structure to bewell mounted and electrically connected to the substrate, such that theelectrical connection quality and reliability of the entiresemiconductor package would not be affected. Moreover, the fabricatedpreformed package structure before being mounted on the substrate issubjected to a burn-in test. Specifically, only the preformed packagestructure that has successfully passed the burn-in test would be mountedon the substrate. As a result, the preformed package structure would notcontain a second chip that is defective or unknown with its quality,such that the conventional known good die (KGD) problem can beeliminated, and the reliability and yield of the entire semiconductorpackage are assured. Additionally, in another preferred embodiment ofthe present invention, a lead frame of the preformed package structurehas a die pad exposed from the first encapsulation body, with a lowersurface of the die pad abutting against the gap between the firstencapsulation body and the first chip, and prior to fabricating thesecond encapsulation body, a thermally conductive adhesive is applied inthe gap between the first encapsulation body and the first chip, suchthat heat generated by the second chip mounted on the die pad can betransmitted via the die pad and the thermally conductive adhesive to thefirst chip and then transmitted via the solder bumps and the substrateto be dissipated out of the semiconductor package. This thus effectivelyimproves the heat dissipating efficiency of the entire semiconductorpackage. Furthermore, the semiconductor package in the present inventionhas a multi-chip structure containing at least the first and secondchips, thereby providing the entire semiconductor package with enhancedelectrical and operational performances.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

FIG. 1 is a cross-sectional view of a multi-chip semiconductor packageaccording to a first preferred embodiment of the present invention;

FIGS. 2A to 2E are schematic diagrams showing a set of steps offabricating the semiconductor package in FIG. 1;

FIGS. 3A to 3F are schematic diagrams showing another set of steps offabricating the semiconductor package in FIG. 1;

FIG. 4 is a cross-sectional view of a multi-chip semiconductor packageaccording to a second preferred embodiment of the present invention;

FIG. 5 (PRIOR ART) is a cross-sectional view of a conventionalmulti-chip semiconductor package; and

FIG. 6 (PRIOR ART) is a cross-sectional view of another conventionalmulti-chip semiconductor package.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As shown in FIG. 1, a multi-chip semiconductor package according to afirst preferred embodiment of the present invention comprises asubstrate 10 having an upper surface 100 and a lower surface 101 opposedto the upper surface 100; at least one first chip 11 mounted on andelectrically connected to the upper surface 100 of the substrate 10 viaa plurality of solder bumps 12 in a flip-chip manner; a preformedpackage structure 13 mounted on and electrically connected to the uppersurface 100 of the substrate 10 via outer leads 143 exposed from a firstencapsulation body 16 of the preformed package structure 13, wherein thefirst encapsulation body 16, the outer leads 143 and the substrate 10form a space S where the first chip 11 is received, and a gap G ispresent between the first chip 11 and the first encapsulation body 16; asecond encapsulation body 17 formed on the upper surface 100 of thesubstrate 10 to encapsulate the first chip 11, the solder bumps 12 andthe preformed package structure 13 and fill the space S and the gap G;and a plurality of solder balls 18 implanted on the lower surface 101 ofthe substrate 10.

The substrate 10 can be a normal substrate having predeterminedcircuitry (not shown) to accommodate both the preformed packagestructure 13 and the first chip 11 (flip chip). The substrate 10 isprimarily made of a resin material such as epoxy resin, polyimide resin,BT (bismaleimide triazine) resin or FR4 resin, etc.

The first chip 11 has an active surface 110 and a non-active surface 111opposed to the active surface 110, wherein a plurality of electronicelements (not shown), electronic circuits (not shown) and bond pads 112are disposed on the active surface 110. The bond pads 112 are bonded tothe plurality of solder bumps 12 to allow the active surface 110 of thefirst chip 11 to be mounted on and electrically connected to the uppersurface 100 of the substrate 10 via the solder bumps 12 in the flip-chipmanner.

The preformed package structure 13 comprises a lead frame 14, at leastone second chip 15 mounted on and electrically connected to the leadframe 14, and the first encapsulation body 16 for encapsulating thesecond chip 15 and a portion of the lead frame 14. The lead frame 14includes a die pad 140 and a plurality of leads 141, wherein each of theleads 141 is composed of an inner lead 142 and an outer lead 143.

The second chip 15 is mounted on the die pad 140 and is electricallyconnected to the inner leads 142 via a plurality of bonding wires 19.The die pad 140 and the inner leads 142 are encapsulated by the firstencapsulation body 16.

Moreover, the first encapsulation body 16 can be made of a same ordifferent conventional resin material as or from the secondencapsulation body 17; for example, a commonly used resin materialincludes epoxy resin and the like.

The multi-chip semiconductor package shown in FIG. 1 can be fabricatedby the procedural steps shown in FIGS. 2A to 2E.

First referring to FIG. 2A, a substrate 10 is provided, which has anupper surface 100 and a lower surface 101 opposed to the upper surface100. The substrate 10 can be a normal substrate having predeterminedcircuitry (not shown), and is primarily made of a resin material such asepoxy resin, polyimide resin, BT (bismaleimide triazine) resin or FR4resin, etc. Since the structure and fabrication of the substrate areboth known in the art, they are not to be further described here.

Referring to FIG. 2B, at least one first chip 11 is provided, which hasan active surface 110 and a non-active surface 111 opposed to the activesurface 110, wherein a plurality of electronic elements (not shown),electronic circuits (not shown) and bond pads 112 are disposed on theactive surface 110. Next, a plurality of solder bumps 12 are formed onthe bond pads 112 of the active surface 110 of the first chip 11. Then,the first chip 11 is mounted on the upper surface 100 of the substrate10 in a flip-chip manner that the active surface 110 of the first chip11 faces downwards and is electrically connected to the upper surface100 of the substrate 10 via the plurality of solder bumps 12. Thefabrication of the first chip and solder bumps is known in the art andthus not to be further detailed herein.

Referring to FIG. 2C, a preformed package structure 13 is mounted on theupper surface 100 of the substrate 10. The preformed package structure13 can be a pre-fabricated lead-frame-based quad flat package (QFP) andsuccessfully passes the conventional burn-in test. The preformed packagestructure 13 comprises a lead frame 14, at least one second chip 15mounted on and electrically connected to the lead frame 14, and a firstencapsulation body 16 for encapsulating the second chip 15 and a portionof the lead frame 14, wherein the first encapsulation body 16 is made ofa conventional resin material such as epoxy resin, etc. The lead frame14 includes a die pad 140 and a plurality of leads 141, wherein each ofthe leads 141 is composed of an inner lead 142 and an outer lead 143.The second chip 15 is mounted on an upper surface of the die pad 140 andis electrically connected to the inner leads 142 via a plurality ofbonding wires 19. The die pad 140, the inner leads 142 and the bondingwires 19 are encapsulated by the first encapsulation body 16, with theouter leads 143 being exposed from the first encapsulation body 16. Theexposed outer leads 143 are used to mount and electrically connect thepreformed package structure 13 to the upper surface 100 of the substrate10 via for example, surface mount technology (SMT), etc. As a result,the first encapsulation body 16 is supported above the first chip 11 andforms a space S together with the outer leads 143 and the substrate 10to receive the first chip 11 therein, and a gap G is present between thefirst encapsulation body 16 and the non-active surface 111 of the firstchip 11. The surface mount technology is known in the art and thus notto be further detailed herein.

Referring to FIG. 2D, a molding process is performed using anencapsulation mold having an upper mold and a lower mold (not shown),wherein the upper mold is formed with a cavity, and the lower mold canbe a flat mold. The substrate 10 mounted with the first chip 11 and thepreformed package structure 13 thereon is placed in the encapsulationmold, wherein the first chip 11 and the preformed package structure 13are received in the cavity of the upper mold, and the substrate 10 isclamped between the upper and lower molds, with the lower surface 101 ofthe substrate 10 abutting against the flat lower mold. Then, aconventional resin material (such as epoxy resin, etc.) is injected intothe cavity of the upper mold to encapsulate the first chip 11, thesolder bumps 12 and the preformed package structure 13 on the uppersurface 100 of the substrate 10, and fill the space S, the gap G betweenthe first chip 11 and the first encapsulation body 16, and gaps betweenthe adjacent solder bumps 12. When the resin material is cured, theencapsulation mold can be removed from the substrate 10, such that asecond encapsulation body 17 is formed on the upper surface 100 of thesubstrate 10. Since the lower surface 101 of the substrate 10 abutsagainst the flat lower mold during molding, no resin material or secondencapsulation body 17 would be formed on the lower surface 101 of thesubstrate 10, and thus the lower surface 101 of the substrate 10 isexposed after the encapsulation mold is removed. The secondencapsulation body 17 can be made of a same or different conventionalresin material as or from the first encapsulation body 16.

Finally, referring to FIG. 2E, a ball-implanting process is carried outto implant a plurality of solder balls 18 on the exposed lower surface101 of the substrate 10. This thus completes fabrication of themulti-chip semiconductor package in the present invention. The solderballs 18 may serve as input/output (I/O) connections of thesemiconductor package to be connected to an external device such as aprinted circuit board (not shown), so as to establish an electricalconnection between the semiconductor package and the external device viathe solder balls 18. The ball-implanting process is known in the art andnot to be further described herein.

In addition, the multi-chip semiconductor package shown in FIG. 1 canalso be fabricated by a batch method with reference to FIGS. 3A to 3F.

First referring to FIG. 3A, a substrate strip 1 is provided, whichcomprises a plurality of integrally formed substrates 10 and has anupper surface 100 and a lower surface 101 opposed to the upper surface100, wherein the adjacent substrates 10 are bordered by dotted cuttinglines shown in the drawing. The substrate strip 1 is formed withpredetermined circuitry (not shown), and is primarily made of a resinmaterial such as epoxy resin, polyimide resin, BT resin or FR4 resin,etc.

Referring to FIG. 3B, a plurality of first chips 11 are provided, eachof the first chips 11 having an active surface 110 and a non-activesurface 111, wherein a plurality of electronic elements (not shown),electronic circuits (not shown) and bond pads 112 are disposed on theactive surface 110 of each of the first chips 11. Then, a plurality ofsolder bumps 12 are formed on the bond pads 112 of the active surface110 of each of the first chips 11. Subsequently, at least one of thefirst chips 11 is mounted on the upper surface 100 of each of thesubstrates 10 in a flip-chip manner that the active surface 110 of thefirst chip 11 faces downwards and is electrically connected to the uppersurface 100 of the corresponding substrate 10 via the solder bumps 12.

Referring to FIG. 3C, a preformed package structure 13 is mounted on theupper surface 100 of each of the substrates 10. The preformed packagestructure 13 can have a structure as that shown in FIG. 2C, comprising alead frame 14, at least one second chip 15 mounted on and electricallyconnected to the lead frame 14, and a first encapsulation body 16 (madeof a resin material such as epoxy resin, etc.) for encapsulating thesecond chip 15 and a portion of the lead frame 14. The lead frame 14includes a die pad 140 and a plurality of leads 141, wherein each of theleads 141 is composed of an inner lead 142 and an outer lead 143. Thesecond chip 15 is mounted on an upper surface of the die pad 140 and iselectrically connected to the inner leads 142 via a plurality of bondingwires 19. The die pad 140, the inner leads 142 and the bonding wires 19are encapsulated by the first encapsulation body 16, with the outerleads 143 being exposed from the first encapsulation body 16. Theexposed outer leads 143 are used to mount and electrically connect thepreformed package structure 13 to the upper surface 100 of each of thesubstrates 10 via for example, surface mount technology (SMT), etc. As aresult, the first encapsulation body 16 of the preformed packagestructure 13 is supported above each of the first chips 11 and forms aspace S together with the outer leads 143 and the correspondingsubstrate 10 to receive the corresponding first chip 11 therein, and agap G is present between the first encapsulation body 16 and thenon-active surface 111 of the corresponding first chip 11.

Referring to FIG. 3D, a molding process is performed to form a secondencapsulation body 17 on the upper surface 100 of the substrate strip 1.First, the substrate strip 1 mounted with the plurality of first chips11 and preformed package structures 13 is placed in an encapsulationmold (not shown), allowing the plurality of first chips 11 and preformedpackage structures 13 to be received in a cavity of the encapsulationmold. Then, a resin material (such as epoxy resin, etc.) is injectedinto the cavity to encapsulate all of the first chips 11, the solderbumps 12 and the preformed package structures 13, and fill all of theforegoing spaces S, the gaps between the first chips 11 and the firstencapsulation bodies 16, and gaps between the adjacent solder bumps 12.When the resin material is cured, the encapsulation mold can be removedfrom the substrate strip 1, and thus the second encapsulation body 17 iscompletely fabricated. The second encapsulation body 17 can be made of asame or different conventional resin material as or from the firstencapsulation body 16.

Subsequently, referring to FIG. 3E, a ball-implanting process is carriedout to implant a plurality of solder balls 18 on the lower surface 101of each of the substrates 10.

Finally, referring to FIG. 3F, a singulation process is performed to cutthe substrate strip 1 and the second encapsulation body 17 along thecutting lines on the substrate strip 1, so as to separate apart theplurality of substrates 10 and form a plurality of individualsemiconductor packages. The singulation process is known in the art andthus not to be further detailed herein. The singulated semiconductorpackages each has the plurality of solder balls 18 that may serve as I/Oconnections of the corresponding semiconductor package to beelectrically connected to an external device such as a printed circuitboard (not shown), so as to establish an electrical connection betweenthe semiconductor package and the external device via the solder balls18.

FIG. 4 shows a multi-chip semiconductor package according to a secondpreferred embodiment of the present invention. As shown in FIG. 4, thissemiconductor package differs from that of the above first embodiment inthat the preformed package structure 13 is a lead-frame-based packagewith an exposed die pad. In particular, a lower surface of the die pad140 of the lead frame 14 is exposed from the first encapsulation body 16and is flush with the first encapsulation body 16. The exposed lowersurface of the die pad 140 abuts against the gap G between the firstchip 11 and the first encapsulation body 16. A thermally conductiveadhesive 2, instead of the second encapsulation body 17 forencapsulating the first chip 11, is applied in the gap G. The thermallyconductive adhesive 2 allows the preformed package structure 13 to bethermally connected via its exposed die pad 140 to the first chip 11,such that heat generated by the second chip 15 mounted on the die pad140 can be transmitted to the first chip 11 and then to the solder bumps12 and the substrate 10 to be dissipated out of the semiconductorpackage. Such additional heat dissipating path can effectively improvethe heat dissipating efficiency of the semiconductor package.

The multi-chip semiconductor package in the second embodiment can befabricated by the steps similar to those shown in FIGS. 2A to 2E or by abatch method similar to that shown in FIGS. 3A to 3F. The fabricationprocesses of the semiconductor package in the second embodiment differfrom those shown in FIGS. 2A to 2E or FIGS. 3A to 3F in that, after thesubstrate 10 is provided and the first chip 11 is mounted on thesubstrate 10 in FIGS. 2A to 2B and FIGS. 3A to 3B, a thermallyconductive adhesive 2 is applied on the non-active surface 111 of thefirst chip 11. Then, a process similar to FIG. 2C or 3C for mounting thepreformed package structure 13 on the substrate 10 is performed, whereinthe exposed lower surface of the die pad 140 and the first encapsulationbody 16 of the preformed package structure 13 are attached to thethermally conductive adhesive 2, making the thermally conductiveadhesive 2 fill the gap G between the first chip 11 and the firstencapsulation body 16. Subsequently, the processes shown in FIGS. 2D to2E or FIGS. 3D to 3F are carried out. Since the thermally conductiveadhesive 2 is filled in the gap G between the first chip 11 and thefirst encapsulation body 16 prior to the molding process of FIG. 2D or3D, the second encapsulation body 17 formed by molding would not fillthe gap G. Further as described above, the provision of thermallyconductive adhesive 2 facilitates dissipation of heat generated by thesecond chip 15 in the preformed package structure 13, therebyeffectively improving the overall heat dissipating efficiency of thesemiconductor package.

The above multi-chip semiconductor package and its fabrication methodsaccording to the present invention allow a substrate to accommodate botha packaged chip and a flip chip. This is accomplished by firstly,electrically connecting a first chip in a flip-chip manner to thesubstrate via a plurality of solder bumps, and then mounting a preformedpackage structure on the substrate, wherein the preformed packagestructure is incorporated with a second chip and has exposed outer leadsthat are mounted and electrically connected to the substrate by surfacemount technology (SMT), such that a first encapsulation body of thepreformed package structure, the exposed outer leads and the substrateform a space where the first chip is received, and the firstencapsulation body is supported above the first chip, with a gap beingpresent between the first encapsulation body and the first chip. Sincethe preformed package structure is electrically connected to thesubstrate by the surface mount technology, the solder bumps locatedbetween the first chip and the substrate would not subject to crackscaused by shocks generated during a wire-bonding process in the priorart. Thus, an underfill process is not required in the present inventionto fill gaps between the adjacent solder bumps located between the firstchip and the substrate. On the other hand, in the present invention, asingle molding process is carried out to form a second encapsulationbody for encapsulating the first chip and the preformed packagestructure as well as filling the gap between the first encapsulationbody and the first chip and the gaps between the adjacent solder bumps.This can prevent predetermined positions on the substrate for mountingthe outer leads of the preformed package structure from contamination bythe underfill process, and assure the preformed package structure to bewell mounted and electrically connected to the substrate, such that theelectrical connection quality and reliability of the entiresemiconductor package would not be affected. Moreover, the fabricatedpreformed package structure before being mounted on the substrate issubjected to a burn-in test. Specifically, only the preformed packagestructure that has successfully passed the burn-in test would be mountedon the substrate. As a result, the preformed package structure would notcontain a second chip that is defective or unknown with its quality,such that the conventional known good die (KGD) problem can beeliminated, and the reliability and yield of the entire semiconductorpackage are assured. Additionally, in another preferred embodiment ofthe present invention, a lead frame of the preformed package structurehas a die pad exposed from the first encapsulation body, with a lowersurface of the die pad abutting against the gap between the firstencapsulation body and the first chip, and prior to fabricating thesecond encapsulation body, a thermally conductive adhesive is applied inthe gap between the first encapsulation body and the first chip, suchthat heat generated by the second chip mounted on the die pad can betransmitted via the die pad and the thermally conductive adhesive to thefirst chip and then transmitted via the solder bumps and the substrateto be dissipated out of the semiconductor package. This thus effectivelyimproves the heat dissipating efficiency of the entire semiconductorpackage. Furthermore, the semiconductor package in the present inventionhas a multi-chip structure containing at least the first and secondchips, thereby providing the entire semiconductor package with enhancedelectrical and operational performances.

The present invention has been described using exemplary preferredembodiments. However, it is to be understood that the scope of theinvention is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangements.The scope of the claims, therefore, should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements.

1-8. (canceled)
 9. A fabrication method of a multi-chip semiconductorpackage, comprising the steps of: providing a substrate having an uppersurface and a lower surface opposed to the upper surface; providing atleast one first chip having an active surface and a non-active surface,and allowing the active surface of the first chip to be mounted on andelectrically connected to the upper surface of the substrate via aplurality of solder bumps; mounting a preformed package structure on theupper surface of the substrate, the preformed package structurecomprising a lead frame, at least one second chip mounted on andelectrically connected to the lead frame, and a first encapsulation bodyfor encapsulating the second chip and a portion of the lead frame, withouter leads of the lead frame being exposed from the first encapsulationbody and mounted on the upper surface of the substrate, wherein thefirst encapsulation body, the exposed outer leads and the substrate forma space where the first chip is received, and a gap is present betweenthe non-active surface of the first chip and the first encapsulationbody; and forming a second encapsulation body on the upper surface ofthe substrate to encapsulate the first chip, the solder bumps and thepreformed package structure.
 10. The fabrication method of claim 9,further comprising a step of implanting a plurality of solder balls onthe lower surface of the substrate.
 11. The fabrication method of claim9, wherein the preformed package structure is mounted on the uppersurface of the substrate by surface mount technology.
 12. Thefabrication method of claim 9, wherein the second chip is electricallyconnected to the lead frame via a plurality of bonding wires.
 13. Thefabrication method of claim 12, wherein the lead frame comprises a diepad and a plurality of leads, each of the leads comprising an inner leadand one of the outer leads, such that the second chip is mounted on anupper surface of the die pad and electrically connected to the innerleads, and the inner leads are encapsulated by the first encapsulationbody.
 14. The fabrication method of claim 13, wherein the die pad isencapsulated by the first encapsulation body.
 15. The fabrication methodof claim 14, wherein the gap between the first chip and the firstencapsulation body is filled with the second encapsulation body.
 16. Thefabrication method of claim 13, wherein a lower surface of the die padis exposed from the first encapsulation body and abuts against the gapbetween the first chip and the first encapsulation body.
 17. Thefabrication method of claim 16, wherein the gap between the first chipand the first encapsulation body is applied with a thermally conductiveadhesive.
 18. A fabrication method of multi-chip semiconductor packages,comprising the steps of: providing a substrate strip, the substratestrip comprising a plurality of substrates and having an upper surfaceand a lower surface opposed to the upper surface; mounting at least onefirst chip on the upper surface of each of the substrates, the firstchip having an active surface and a non-active surface; and allowing theactive surface of the first chip to be electrically connected to theupper surface of each of the substrates via a plurality of solder bumps;mounting a preformed package structure on the upper surface of each ofthe substrates, the preformed package structure comprising a lead frame,at least one second chip mounted on and electrically connected to thelead frame, and a first encapsulation body for encapsulating the secondchip and a portion of the lead frame, with outer leads of the lead framebeing exposed from the first encapsulation body and mounted on the uppersurface of each of the substrates, wherein the first encapsulation body,the exposed outer leads and the corresponding substrate form a spacewhere the first chip is received, and a gap is present between thenon-active surface of the first chip and the first encapsulation body;forming a second encapsulation body on the upper surface of thesubstrate strip to encapsulate all of the first chips, the solder bumpsand the preformed package structures; implanting a plurality of solderballs on the lower surface of the substrate strip; and performing asingulation process to cut the second encapsulation body and thesubstrate strip so as to separate apart the plurality of substrates andform a plurality of the individual semiconductor packages.
 19. Thefabrication method of claim 18, wherein the preformed package structureis mounted on each of the substrates by surface mount technology. 20.The fabrication method of claim 18, wherein the second chip iselectrically connected to the lead frame via a plurality of bondingwires.
 21. The fabrication method of claim 20, wherein the lead framecomprises a die pad and a plurality of leads, each of the leadscomprising an inner lead and one of the outer leads, such that thesecond chip is mounted on an upper surface of the die pad andelectrically connected to the inner leads, and the inner leads areencapsulated by the first encapsulation body.
 22. The fabrication methodof claim 21, wherein the die pad is encapsulated by the firstencapsulation body.
 23. The fabrication method of claim 22, wherein thegap between the first chip and the first encapsulation body is filledwith the second encapsulation body.
 24. The fabrication method of claim21, wherein a lower surface of the die pad is exposed from the firstencapsulation body and abuts against the gap between the first chip andthe first encapsulation body.
 25. The fabrication method of claim 24,wherein the gap between the first chip and the first encapsulation bodyis applied with a thermally conductive adhesive.